Sashank Krishnamurthy

Assistant Professor, IIT Madras

Email: sashank@ee.iitm.ac.in

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Research

My research focuses on integrated transceiver architectures for next-generation communication systems, with specific emphasis on interference-resilient wireless receivers based on N-path filtering and high-speed wireline and optical links for advanced computing platforms.

Wireless Integrated Circuits

Interference-Resilient Receivers Using N-Path Techniques

Low-Power IoT / BLE Receivers

This work focuses on ultra-low-power receiver architectures for BLE and IoT applications operating in dense ISM bands. These designs use N-path filtering and translational feedback concepts to achieve strong interference resilience at very low power levels.

Higher-Order N-Path Filters

N-path filters translate low-pass baseband impedances to RF, enabling tunable bandpass filtering simply by adjusting the LO frequency applied to the switch network. This work focuses on extending “vanilla” N-path filters to achieve sharper selectivity and stronger rejection of interferers.

We pursue two broad approaches. The first uses higher-order baseband driving-point impedances to synthesize higher-order bandpass responses; as part of this work, we demonstrated the first-ever realization of a third-order all-pole driving-point impedance in an N-path filter system. The second approach constructs higher-order N-path filters by subtracting the responses of staggered low-order NPFs, developed in collaboration with Ashoke Ravi (Intel), Ofir Degani (Intel), Soumya Gupta (OSU), and Arun Natarajan (Yale).

Most of the work so far has focused on sub-6 GHz 5G and next-generation Wi-Fi bands. Extending these techniques to 6G / FR3 (7–24 GHz) operation is a promising avenue for future research.

N-Path Filtering at mm-Wave Frequencies

This work explores the extension of N-path filters to mm-wave receiver front-ends, enabling frequency-selective behavior at much higher operating frequencies than traditionally associated with switched-capacitor or mixer-first architectures. A central challenge is the generation of narrow LO pulses required to drive the N-path switches and the development of circuit techniques to address this without compromising the noise figure or the linearity advantages observed at lower frequencies.

Our work demonstrated a 28 nm CMOS prototype operating at 35 GHz, showing an order-of-magnitude improvement in in-band linearity compared to state-of-the-art solutions, while maintaining a modest noise figure. These results indicate that N-path filtering remains a strong candidate for mm-wave digital massive-MIMO array front-ends.

High-Speed Optical and Wireline Links

This thrust focuses on CMOS transceivers for short-reach, high-bandwidth electrical and long-reach optical interconnects used in next-generation computing systems. The work targets low energy per bit, high bandwidth density, and co-packaged integration with high-performance integrated circuits.

High-Speed Co-Packaged VCSEL-Based Optical Links

Co-packaged optics integrates the optical engine with the switch ASIC, eliminating bandwidth and reach limitations of pluggable modules and electrical interconnects while enabling energy-efficient datacenter connectivity using low-cost multimode VCSELs. In joint work with Susnata Mondal, Junyi Qiu, and Mozhgan Mansuri, our work demonstrates two energy-efficient CPO transceivers: a 2.9 pJ/b 50 Gb/s NRZ link and a 0.9 pJ/b 108 Gb/s PAM-4 optical engine. These results are enabled through transmitter/VCSEL driver design, low-power clocking architectures, matching networks that mitigate co-packaging parasitics, and receiver circuits leveraging high-linearity TIA front-ends, low-power equalization, and high-speed low-noise latch architectures.

Next-Generation Die-to-Die Wireline Links